Efficient cycle-accurate simulation of the UltraSPARC III CPU

Peter Strazdins*, Bill Clarke, Andrew Over

*Corresponding author for this work

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    2 Citations (Scopus)

    Abstract

    This paper presents a novel technique for cycleaccurate simulation of the Central Processing Unit (CPU) of a modern superscalar processor, the Ultra-SPARC III Cu processor. The technique is based on adding a module to an existing fetch-decode-execute style of CPU simulator, rather than the traditional method of fully modelling the CPU microarchitecture. It is also suitable for accurate SMP modelling. The main functions of the module are the simulation of instruction grouping, register interlocks and the store buffer. Its simple table-driven implementation permits easy modification for exploring microarchitectural variations. The technique results in a 40% loss of simulation speed, instead of a 10 times or greater performance loss by fully implementing the detailed micro-architecture. The technique is validated against an actual UltraSPARC III Cu processor, and achieves high levels of accuracy over a range of scientific benchmarks.

    Original languageEnglish
    Title of host publicationComputer Science 2007 - Proceedings of the 13th Australasian Computer Science Conference, ACSC 2007
    Pages221-228
    Number of pages8
    Publication statusPublished - 2007
    Event30th Australasian Computer Science Conference, ACSC 2007 - Ballarat, VIC, Australia
    Duration: 30 Jan 20072 Feb 2007

    Publication series

    NameConferences in Research and Practice in Information Technology Series
    Volume62
    ISSN (Print)1445-1336

    Conference

    Conference30th Australasian Computer Science Conference, ACSC 2007
    Country/TerritoryAustralia
    CityBallarat, VIC
    Period30/01/072/02/07

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