TY - JOUR
T1 - Electrical characterization of impurity-free disordering-induced defects in n-GaAs using native oxide layers
AU - Deenapanray, P. N.K.
AU - Tan, H. H.
AU - Jagadish, C.
PY - 2003/4
Y1 - 2003/4
N2 - Defects created in rapid thermally annealed n-GaAs epilayers capped with native oxide layers have been investigated using deep-level transient spectroscopy (DLTS). The native oxide layers were formed at room temperature using pulsed anodic oxidation. A hole trap H0, due to either interface states or injection of interstitials, is observed around the detection limit of DLTS in oxidized samples. Rapid thermal annealing introduces three additional minority-carrier traps H1 (EV + 0.44 eV), H2 (EV + 0.73 eV), and H3 (EV + 0.76 eV). These hole traps are introduced in conjunction with electron traps S1 (EC - 0.23 eV) and S2 (EC - 0.45 eV), which are observed in the same epilayers following disordering using SiO2 capping layers. We also provide evidence that a hole trap whose DLTS peak overlaps with that of EL2 is present in the disordered n-GaAs layers. The mechanisms through which these hole traps are created are discussed. Capacitance-voltage measurements reveal that impurity-free disordering using native oxides of GaAs produced higher free-carrier compensation compared to SiO2 capping layers.
AB - Defects created in rapid thermally annealed n-GaAs epilayers capped with native oxide layers have been investigated using deep-level transient spectroscopy (DLTS). The native oxide layers were formed at room temperature using pulsed anodic oxidation. A hole trap H0, due to either interface states or injection of interstitials, is observed around the detection limit of DLTS in oxidized samples. Rapid thermal annealing introduces three additional minority-carrier traps H1 (EV + 0.44 eV), H2 (EV + 0.73 eV), and H3 (EV + 0.76 eV). These hole traps are introduced in conjunction with electron traps S1 (EC - 0.23 eV) and S2 (EC - 0.45 eV), which are observed in the same epilayers following disordering using SiO2 capping layers. We also provide evidence that a hole trap whose DLTS peak overlaps with that of EL2 is present in the disordered n-GaAs layers. The mechanisms through which these hole traps are created are discussed. Capacitance-voltage measurements reveal that impurity-free disordering using native oxides of GaAs produced higher free-carrier compensation compared to SiO2 capping layers.
UR - http://www.scopus.com/inward/record.url?scp=0037389377&partnerID=8YFLogxK
U2 - 10.1007/s00339-002-1826-5
DO - 10.1007/s00339-002-1826-5
M3 - Article
SN - 0947-8396
VL - 76
SP - 961
EP - 964
JO - Applied Physics A: Materials Science and Processing
JF - Applied Physics A: Materials Science and Processing
IS - 6
ER -