TY - GEN
T1 - How small can it be?
T2 - 17th IEEE International Conference on High Performance Computing and Communications, IEEE 7th International Symposium on Cyberspace Safety and Security and IEEE 12th International Conference on Embedded Software and Systems, HPCC-ICESS-CSS 2015
AU - Lee, Chung
AU - Strazdins, Peter
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/11/23
Y1 - 2015/11/23
N2 - I/O processing in virtualization is expensive. It significantly slows down application performance running on virtual machines due to frequent context switches and resource contentions. There are several methods to address the problem. One solution is the side-core approach to carry out virtualization I/O processing on a dedicated core, which offers close to bare-metal performance, without sacrificing important virtualization features. Although the number of cores is continually increasing and the financial cost per core is dropping, considering the characteristics of I/O processing, the side-core approach can be more efficient with an asymmetric multi-processor (AMP) rather than a symmetric multi-processor (SMP). However, no thorough study has been performed to identify the requirements for the AMP to off-load the virtualization I/O tasks. In this paper, we examine various processor features, study behaviour of three different processors, and identify the most cost-efficient parameters for a side-core, both in terms of the financial cost and the number transistors. From our experimental analysis, we conclude that a narrow, fast (high clock) in-order pipeline, with small first/second level caches without hardware data prefetch, and a simple branch prediction unit are the desired features in a dedicated side-core for I/O processing. We estimate that this small side-core should consist of one fourth the transistor budget and perform I/O processing with only a 10% performance loss at the same frequency, compared to a big side-core.
AB - I/O processing in virtualization is expensive. It significantly slows down application performance running on virtual machines due to frequent context switches and resource contentions. There are several methods to address the problem. One solution is the side-core approach to carry out virtualization I/O processing on a dedicated core, which offers close to bare-metal performance, without sacrificing important virtualization features. Although the number of cores is continually increasing and the financial cost per core is dropping, considering the characteristics of I/O processing, the side-core approach can be more efficient with an asymmetric multi-processor (AMP) rather than a symmetric multi-processor (SMP). However, no thorough study has been performed to identify the requirements for the AMP to off-load the virtualization I/O tasks. In this paper, we examine various processor features, study behaviour of three different processors, and identify the most cost-efficient parameters for a side-core, both in terms of the financial cost and the number transistors. From our experimental analysis, we conclude that a narrow, fast (high clock) in-order pipeline, with small first/second level caches without hardware data prefetch, and a simple branch prediction unit are the desired features in a dedicated side-core for I/O processing. We estimate that this small side-core should consist of one fourth the transistor budget and perform I/O processing with only a 10% performance loss at the same frequency, compared to a big side-core.
KW - Heterogeneous processor
KW - Networking
KW - Performance evaluation
KW - VM I/O
UR - http://www.scopus.com/inward/record.url?scp=84961737537&partnerID=8YFLogxK
U2 - 10.1109/HPCC-CSS-ICESS.2015.302
DO - 10.1109/HPCC-CSS-ICESS.2015.302
M3 - Conference contribution
T3 - Proceedings - 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security and 2015 IEEE 12th International Conference on Embedded Software and Systems, HPCC-CSS-ICESS 2015
SP - 455
EP - 462
BT - Proceedings - 2015 IEEE 17th International Conference on High Performance Computing and Communications, 2015 IEEE 7th International Symposium on Cyberspace Safety and Security and 2015 IEEE 12th International Conference on Embedded Software and Systems, HPCC-CSS-ICESS 2015
PB - Institute of Electrical and Electronics Engineers Inc.
Y2 - 24 August 2015 through 26 August 2015
ER -