Low-Variance Memristor-Based Multi-Level Ternary Combinational Logic

Xiao Yuan Wang*, Chuan Tao Dong, Peng Fei Zhou, Sanjoy Kumar Nandi, Shimul Kanti Nath, Robert G. Elliman, Herbert Ho Ching Iu, Sung Mo Kang, Jason K. Eshraghian

*Corresponding author for this work

    Research output: Contribution to journalArticlepeer-review

    14 Citations (Scopus)


    This paper presents a series of multi-stage hybrid memristor-CMOS ternary combinational logic stages that are optimized for reducing silicon area occupation. Prior demonstrations of memristive logic are typically constrained to single-stage logic due to the variety of challenges that affect device performance. Noise accumulation across subsequent stages can be amortized by integrating ternary logic gates, thus enabling higher density data transmission, where more complex computation can take place within a smaller number of stages when compared to single-bit computation. We present the design of a ternary half adder, a ternary full adder, a ternary multiplier, and a ternary magnitude comparator. These designs are simulated in SPICE using the broadly accessible Knowm memristor model, and we perform experimental validation of individual stages using an in-house fabricated Si-doped HfOx memristor which exhibits low cycle-to-cycle variation, and thus contributes to robust long-term performance. We ultimately show an improvement in data density in each logic block of between 5.2 × - 17.3 × , which also accounts for intermediate voltage buffering to alleviate the memristive loading problem.

    Original languageEnglish
    Pages (from-to)2423-2434
    Number of pages12
    JournalIEEE Transactions on Circuits and Systems I: Regular Papers
    Issue number6
    Publication statusPublished - 1 Jun 2022


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