@inproceedings{26eb807617e547b196513c2c263a1907,
title = "Programming the adapteva epiphany 64-core network-on-chip coprocessor",
abstract = "With energy efficiency and power consumption being the primary impediment in the path to exascale systems, low-power high performance embedded systems are of increasing interest. The Parallella System-on-module (SoM) created by Adapteva combines the Epiphany-IV 64-core coprocessor with a host ARM processor housed in a Zynq System-on-chip. The Epiphany integrates low-power RISC cores on a 2D mesh network and promises up to 70 GFLOPS/Watt of processing efficiency. However, with just 32 KB of memory per eCore for storing both data and code, and only low level inter-core communication support, programming the Epiphany system presents several challenges. In this paper we evaluate the performance of the Epiphany system for a variety of basic compute and communication operations. Guided by this data we explore various strategies for implementing stencil based application codes on the Epiphany system. With future systems expected to house 4096 eCores, the merits of the Epiphany architecture as a path to exascale is compared to other competing power efficient systems.",
keywords = "Epiphany, Network-on-chip, Parallella, Stencil",
author = "Anish Varghese and Bob Edwards and Gaurav Mitra and Rendell, {Alistair P.}",
note = "Publisher Copyright: {\textcopyright} 2014 IEEE.; 28th IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2014 ; Conference date: 19-05-2014 Through 23-05-2014",
year = "2014",
month = nov,
day = "27",
doi = "10.1109/IPDPSW.2014.112",
language = "English",
series = "Proceedings - IEEE 28th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2014",
publisher = "IEEE Computer Society",
pages = "984--992",
booktitle = "Proceedings - IEEE 28th International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2014",
address = "United States",
}