Surface topography in mechanical polishing of 6H-SiC (0001) substrate

Ling Yin*, Han Huang

*Corresponding author for this work

    Research output: Chapter in Book/Report/Conference proceedingConference contributionpeer-review

    2 Citations (Scopus)

    Abstract

    Silicon carbide (SiC) single crystals have been used as the substrates of a new generation of wide band-gap semiconductors due to their unparalleled combination of high breakdown voltage, extreme temperature tolerance, mobility and radiation hardness. For their applications, the SiC substrates need to be machined with nanometric surface quality as well as high form accuracy. However, the superior properties of the materials render their machinability extremely difficult. In this paper, we report the form error and surface roughness of the 6H-SiC (0001) substrate mechanically polished using 3 μm diamond powders in two different polishing processes. One process was concentrated-load polishing; the other was surface polishing. The polished surfaces were evaluated using white light interferometry and atomic force microscopy (AFM) for assessment of two- and three-dimensional topographies including form error and surface roughness. We found that a large form error was produced on the 6H-SiC (0001) substrate in the concentrated-load polishing. The root-mean-square (RMS) surface roughness of approximately 4 nm was resulted. Surface polishing of the 6H-SiC (0001) substrate remarkably improved form accuracy. The RMS surface roughness of approximately 2.5 nm was obtained.

    Original languageEnglish
    Title of host publicationMicroelectronics
    Subtitle of host publicationDesign, Technology, and Packaging III
    DOIs
    Publication statusPublished - 2008
    EventMicroelectronics: Design, Technology, and Packaging III - Canberra, ACT, Australia
    Duration: 5 Dec 20077 Dec 2007

    Publication series

    NameProceedings of SPIE - The International Society for Optical Engineering
    Volume6798
    ISSN (Print)0277-786X

    Conference

    ConferenceMicroelectronics: Design, Technology, and Packaging III
    Country/TerritoryAustralia
    CityCanberra, ACT
    Period5/12/077/12/07

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