The Nanoscopic Electronic Structure Shift Induced by Anions at Surfaces (NESSIAS) to replace doping in nano-Si for VLSI (poster)

The NESSIAS causes the electronic structure of SiO2- versus Si3N4-coated low nanoscale intrinsic silicon (Si) to shift away from versus toward the vacuum level Evac [1-5]. The experimentally derived impact length into Si of dNESSIAS of 1.4 nm/ 2.8 nm/ 4.2 nm for nanowells (NWells)/ nanowires (NWires)/ nanocrystals (NCs) renders Si NWells with dWell ≤ 2.8 nm, NWires with dWire ≤ 5.6 nm, and NCs with dNC ≤ 8.4 nm to be dominated by NESSIAS [4]. We explain the origin of NESSIAS by the quantum chemical properties of the elements involved, and delimit it against known interface effects such as interface dipoles or the push-back/pillow effect. Deriving an analytic quantum-chemical parameter Λ to predict the highest occupied energy level of nano-Si, we can predict the energy offset of nano-Si as a function of its dielectric embedding (boride, carbide, nitride, oxide, fluoride, sulfide) [5]. Such predictions are confirmed by various hybrid-density functional calculations carried out with Si nanocrystals (NCs) over a wide size range.
First experimental data of Si nanowells (NWells) [5,6] embedded in SiO2 versus Si3N4 were measured by X-ray absorption spectroscopy in total fluorescence yield mode (XAS-TFY), complemented by ultraviolet photoelectron spectroscopy (UPS), characterizing their conduction band and valence band edge energies EC and EV, respectively. Band offsets of ΔEC = 0.56 eV and ΔEV = 0.89 eV were measured for 1.9 nm thick Si NWells in SiO2 versus Si3N4, demonstrating an intrinsic Si type II homojunction [5].
This p/n junction generated by NESSIAS eliminates any deteriorating impact of impurity dopants in nano-Si – density fluctuations, self-purification and clustering, out-diffusion, finite thermal energy (temperature) required for dopant ionization, loss of power (heat generation) and carrier mobility by inelastic Coulomb scattering. As a result, the NESSIAS offers undoped ultrasmall Si electronic devices with much reduced physical gate lengths and CMOS-compatible materials and logic operating with ultra-low power demand and full cryo-functionality [7]. A strong preference of nano-Si for holes (p-type) or electrons (n-type) is simply achieved by Si3N4- or SiO2 coating.
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