Tunnel junctions in a III–V nanowire by surface engineering

Salman Nadar, Chloé Rolland, Jean François Lampin, Xavier Wallart, Philippe Caroff*, Renaud Leturcq

*Corresponding author for this work

    Research output: Contribution to journalArticlepeer-review

    12 Citations (Scopus)

    Abstract

    We demonstrate a simple way of fabricating high performance tunnel devices from p-doped InAs nanowires by tailoring the n-doped surface accumulation layer inherent to InAs surfaces. By using appropriate ammonium sulfide based surface passivation before metallization without any further thermal treatment, we demonstrate characteristics of tunnel p-n junctions, namely Esaki and backward diodes, with figures of merit better than previously published for InAs homojunctions. The further optimization of both the surface doping, in a quantitative way, and the device geometry allows us to demonstrate that these nanowire-based technologically-simple diodes have promising direct current characteristics for integrated high frequency detection or generation.

    [Figure not available: see fulltext.]

    Original languageEnglish
    Pages (from-to)980-989
    Number of pages10
    JournalNano Research
    Volume8
    Issue number3
    DOIs
    Publication statusPublished - Mar 2015

    Fingerprint

    Dive into the research topics of 'Tunnel junctions in a III–V nanowire by surface engineering'. Together they form a unique fingerprint.

    Cite this